At the end of Fall 2009, myself, Chris Conwill, and Daniel Egert created an IC design for an analog audio compressor with an in-line gate. It was designed for IBM’s 0.13um CMOS process, so it uses a 1.2V power supply and draws under 500 uW of power.
Granted, with a supply of 1.2V our compressor isn’t exactly intended for pro-audio. Instead, its extremely low power consumption makes it perfect for battery-operated applications such as hearing aids or cell phones. By putting this compressor just before the ADC, you can get better SNDR on the digital end (since the input has a narrower dynamic range) and save precious DSP time for more complex tasks.
The gain reduction is achieved by a VCA that operates over a log-linear range of 60-dB (ie 60 dB of potential gain reduction). Also, we designed it to have a fixed ratio between the attack time and release times (1:10 for comp, 1:100 for gate). The absolute attack/release times are set by external capacitors. The compression ratio is currently set to be about 2.6:1, but can be adjusted by changing an external resistor value.
Below are some simulations of our circuit using a short recording of a male voice as an input.
Input
—The raw signal, measured just before entering the compressor (to account for any weirdness that could have happened between the original audio and Cadence’s actual simulated signal.
Compressed
—Compression only. I used a fairly low threshold of about -20dBFS (relative to the highest peak of the input signal), so the compressor’s action is more obvious. Attack time = 10ms, Release time = 100ms, Ratio = 2.6:1
Gated
—Gating only. I used a fairly high threshold of about -34dBFS, for the same reason as before. Attack time = 1ms, Release time = 100ms.
Compressed & Gated
—Simultaneous compression and gating. Same settings as before, just showing the two functions working together.
At the beginning of the winter semester, we decided to continue work on this project. Professor Flynn has offered to help get our design fabricated (whom we cannot thank enough), so if all goes well we will have a real chip to test by the end of 2010.
